02. Position Type: Employee
03. Job Description:
The engineer will be required to perform the following ASIC design tasks:
- Block level layout implementation and timing closure
- Static Timing/Crosstalk Analysis and timing closure
- Synthesis/Physical Synthesis
- Power/IR/EM analysis
- Physical verification (LVS/DRC/ERC)
- ECO implementation
04. Requirements:
- Understanding of chip layout/physical design concepts, methodologies and flows (i.e. floorplanning, power planning, power/IR/EM analysis, custom routing, pad ring etc.)
- Understanding of static timing and crosstalk/noise analysis and timing closure concepts, methodologies and flows.
- Understanding of RTL/gate synthesis concepts, methodologies and flows.
- Experience with the following areas of physical design:
- RTL/gate synthesis
- Floorplanning, place and route
- Static timing/crosstalk analysis
- Physical verification
- Power/IR/EM analysis
- Experience with following layout CAD tools:
- Synthesis: Design Compiler or Genus
- Place & Route: ICC2 or FusionCompiler or Innovus
- Static timing: Primetime or Tempus
05. Benefit:
- Competitive salary and benefits package.
- Opportunity for growth and advancement within the company.
- Chance to work on innovative projects and make a meaningful impact in the automotive industry.
06. Contact: HR@vina-aspire.com
Vina Aspire là Công ty công nghệ cao, tư vấn, cung cấp các giải pháp, dịch vụ CNTT, An ninh mạng, bảo mật & an toàn thông tin tại Việt Nam. Đội ngũ của Vina Aspire gồm những chuyên gia, cộng tác viên giỏi, có trình độ, kinh nghiệm và uy tín cùng các nhà đầu tư, đối tác lớn trong và ngoài nước chung tay xây dựng.
Các Doanh nghiệp, tổ chức có nhu cầu liên hệ Công ty Vina Aspire theo thông tin sau:
Email: info@vina-aspire.com | Website: www.vina-aspire.com
Tel: +84 944 004 666 | Fax: +84 28 3535 0668
Vina Aspire – Vững bảo mật, trọn niềm tin
